Aiwa XR-DV700 Service Manual download pdf (Page 79)

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Pin No. Pin Name I/O Description

IC DESCRIPTION-10/10 (CS49326)-1/2

1

2

3

4

5

6

7

8-11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

VD1

DGND1

AUDATAA3/XMT958

______

WR

_____

RD

SCDIN

SCCLK

GPI07-04

VD2

DGND2

T/M GPI03

C GPI02

B GPI01

A GPI00

_____

CS

SCDIO

______________________________

ABOOT/INTREQ

_________________

EXTMEM

SDATAN1

VD3

DGND3

SCLKLN1

LRCLKN1

SDATAN2

SCLKN2

LRCLKN2

CLKIN

CLKSEL

FILT2

FILT1

VA

AGND

____________

RESET

DD

DC

AUDATA2

—

—

O

I

I

I

I

I

—

—

I

I

I

I

I

O

O

I

I

—

—

I

I

I

I

I

I

I

—

—

—

—

I

—

—

O

Digital positive supply.

Digital ground.

SPDIF transmitter output,digital audio output. (Not connected)

Host write storobe. (Pull down)

Host parallel output enable. (Pull up)

SPI serial control data input.

Serial control port clock.

These pins can act as general-purpose input pins that can be individually configured and

controlled by the DSP. (Pull up)

Digital positive supply.

Digital ground.

These pins can act as general-purpose input pins that can be individually configured and

controlled by the DSP. (Pull up)

These pins can act as general-purpose input pins that can be individually configured and

controlled by the DSP. (Pull up)

These pins can act as general-purpose input pins that can be individually configured and

controlled by the DSP. (Pull up)

These pins can act as general-purpose input pins that can be individually configured and

controlled by the DSP. (Pull up)

Host parallel chip select,host serial SPI chip select.

Serial control port data input and output pin.

Automatic boot enable,control port interrupt request.

External memory chip select. (Pull up)

PCM audio data input number one.

Digital positive supply.

Digital ground.

PCM audio input bit clock.

PCM audio input sample rate clock.

PCM audio data input number two.

PCM audio input bit clock.

PCM audio input sample rate clock.

Master clock input.(Pull down)

DSP clock slect.(Pull down)

Phase-locked loop filter.

Phase-locked loop filter. (Pull down)

Analog positive supply.

Analog ground.

Asynchronous active-low master reset input.

This pin is reserved. (Pull up)

This pin is reserved. (Pull up)

Digital audio output 2.

1 2 ... 74 75 76 77 78 79 80 81 82 83 84 ... 89 90

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