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Aiwa LCX-K277 User Manual Page 27

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39
FOK
FSW
MON
MDP
MDS
LOCK
NC
VCOO
VCOI
TEST
PDO
VSS
PWMI
V16M
VCTL
VPCO
VCKI
FILO
FILI
PCO
AVSS
CLTV
AVDD
RF
BIAS
ASYI
ASYO
ASYE
NC
PSSL
WDCK
LRCK
VDD
DA16
DA15
DA14
DA13
DA12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
IC, CXD2540Q
Pin No. Pin Name I/O Description
I
O
O
O
O
O
—
O
I
I
O
—
I
O
I
O
I
O
I
O
—
I
—
I
I
I
O
I
—
I
O
O
—
O
O
O
O
O
Focus OK input. Used for SENS output and the servo auto sequencer.
Spindle motor output filter switching output.
Spindle motor on/off control output.
Spindle motor servo control.
High, when sampled value of GFS at 460Hz is high.
Low, when sampled value of GFS at 460Hz is low by 8 times successively.
Not used.
Analog EFM PLL oscillation circuit output.
Analog EFM PLL oscillation circuit input. fLOCK=8.6436MHz.
TEST pin.
Analog EFM PLL charge pump output.
GND.
Spindle motor external control input.
VCO2 oscillation output for the wide-band EFM PLL.
VCO2 control voltage input for the wide-band EFM PLL.
Wide-band EFM PLL charge pump output.
VCO2 oscillation input for the wide-band EFM PLL.
Multiplier PLL (slave=digital PLL) filter output.
Multiplier PLL filter input.
Multiplier PLL charge pump output.
Analog GND.
Multiplier VCO1 control voltage input.
Analog power supply (5V).
EFM signal input.
Constant current input of the asymmetry circuit.
Asymmetry comparator voltage input.
EFM full-swing output.
Low: asymmetry circuit off; high: asymmetry circuit on.
Not used.
Audio data output mode switching input. Low: serial output; high: parallel output.
D/A interface for 48-bit slot. Word clock f=2Fs.
D/A interface for 48-bit slot. LR clock f=Fs.
Power supply (5V).
DA16 (MSB) output when PSSL=1.
48-bit slot serial data (two’s complement, MSB first) when PSSL=0.
DA15 output when PSSL=1. 48-bit slot bit clock when PSSL=0.
DA14 output when PSSL=1.
64-bit slot serial data (two’s complement, LSB first) when PSSL=0.
DA13 output when PSSL=1. 64-bit slot bit clock when PSSL=0.
DA12 output when PSSL=1. 64-bit slot LR clock when PSSL=0.
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